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lt1720/lt1721 1 17201fc typical application description dual/quad, 4.5ns, single supply 3v/5v comparators with rail-to-rail outputs the lt ? 1720/lt1721 are ultrafast tm dual/quad compara- tors optimized for single supply operation, with a supply voltage range of 2.7v to 6v. the input voltage range extends from 100mv below ground to 1.2v below the supply volt- age. internal hysteresis makes the lt1720/lt1721 easy to use even with slow moving input signals. the rail-to-rail outputs directly interface to ttl and cmos. alternatively, the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels. the lt1720 is available in three 8-pin packages; three pins per comparator plus power and ground. in addition to so and msop packages, a 3mm 3mm low pro? le (0.8mm) dual ? ne pitch leadless package (dfn) is available for space limited applications. the lt1721 is available in the 16-pin ssop and s packages. the pinouts of the lt1720/lt1721 minimize parasitic effects by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails. the lt1720/lt1721 are ideal for systems where small size and low power are paramount. 2.7v to 6v crystal oscillator with ttl/cmos output l , lt, ltc and ltm are registered trademarks of linear technology corporation. ultafast is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. features applications n high speed differential line receiver n crystal oscillator circuits n window comparators n threshold detectors/discriminators n pulse stretchers n zero-crossing detectors n high speed sampling circuits n ultrafast: 4.5ns at 20mv overdrive 7ns at 5mv overdrive n low power: 4ma per comparator n optimized for 3v and 5v operation n pinout optimized for high speed ease of use n input voltage range extends 100mv below negative rail n ttl/cmos compatible rail-to-rail outputs n internal hysteresis with speci? ed limits n low dynamic current drain; 15a/(v-mhz), dominated by load in most circuits n tiny 3mm 3mm 0.75mm dfn package (lt1720) propagation delay vs overdrive C + c1 1/2 lt1720 2.7v to 6v 2k 620 220 1mhz to 10mhz crystal (at-cut) 2k 17201 ta01 0.1f 1.8k output ground case overdrive (mv) 0 delay (ns) 30 50 17201 ta02 10 20 40 8 7 6 5 4 3 2 1 0 25c v step = 100mv v cc = 5v c load = 10pf rising edge (t pdlh ) falling edge (t pdhl )
lt1720/lt1721 2 17201fc absolute maximum ratings supply voltage, v cc to gnd ........................................7v input current ....................................................... 10ma output current (continuous) ............................. 20ma junction temperature .......................................... 150c (dd package) .................................................... 125c lead temperature (soldering, 10 sec) .................. 300c (note 1) top view dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 4 3 2 1 +in a Cin a Cin b +in b v cc out a out b gnd 9 t jmax = 125c, ja = 160c/w underside metal internally connected to gnd 1 2 3 4 +in a Cin a Cin b +in b 8 7 6 5 v cc out a out b gnd top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 230c/w top view v cc out a out b gnd +in a Cin a Cin b +in b s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 t jmax = 150c, ja = 200c/w 1 2 3 4 5 6 7 8 top view gn package 16-lead narrow plastic ssop s package 16-lead plastic so 16 15 14 13 12 11 10 9 Cin a +in a gnd out a out b gnd +in b Cin b Cin d +in d v cc out d out c v cc +in c Cin c t jmax = 150c, ja = 135c/w (gn) t jmax = 150c, ja = 115c/w (s) pin configuration storage temperature range ................... C65c to 150c (dd package) ..................................... C65c to 125c operating temperature range c grade ................................................... 0c to 70c i grade ............................................... C40c to 85c
lt1720/lt1721 3 17201fc electrical characteristics symbol parameter conditions min typ max units v cc supply voltage l 2.7 6 v i cc supply current (per comparator) v cc = 5v v cc = 3v l l 4 3.5 7 6 ma ma v cmr common mode voltage range (note 2) l ?0.1 v cc ? 1.2 v v trip + input trip points (note 3) l ?2.0 ?3.0 5.5 6.5 mv mv v trip ? input trip points (note 3) l ?5.5 ?6.5 2.0 3.0 mv mv v os input offset voltage (note 3) l 1.0 3.0 4.5 mv mv v hyst input hysteresis voltage (note 3) l 2.0 3.5 7.0 mv v os /t input offset voltage drift l 10 v/c i b input bias current l ?6 0 a i os input offset current l 0.6 a cmrr common mode rejection ratio (note 4) l 55 70 db psrr power supply rejection ratio (note 5) l 65 80 db a v voltage gain (note 6) v oh output high voltage i source = 4ma, v in = v trip + + 10mv l v cc ? 0.4 v v ol output low voltage i sink = 10ma, v in = v trip ? ? 10mv l 0.4 v t pd20 propagation delay v overdrive = 20mv (note 7) l 4.5 6.5 8.0 ns ns t pd5 propagation delay v overdrive = 5mv (notes 7, 8) l 710 13 ns ns the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v cm = 1v, c out = 10pf, v overdrive = 20mv, unless otherwise speci? ed. order information lead free finish tape and reel part marking* package description temperature range lt1720cdd#pbf lt1720cdd#trpbf laav 8-lead (3mm 3mm) plastic dfn 0c to 70c lt1720idd#pbf lt1720idd#trpbf laav 8-lead (3mm 3mm) plastic dfn ?40c to 85c lt1720cms8#pbf lt1720cms8#trpbf ltds 8-lead plastic msop 0c to 70c lt1720ims8#pbf lt1720ims8#trpbf ltacw 8-lead plastic msop ?40c to 85c lt1720cs8#pbf lt1720cs8#trpbf 1720 8-lead plastic so 0c to 70c lt1720is8#pbf lt1720is8#trpbf 1720i 8-lead plastic so ?40c to 85c lt1721cgn#pbf lt1721cgn#trpbf 1721 16-lead narrow plastic ssop 0c to 70c lt1721ign#pbf lt1721ign#trpbf 1721i 16-lead narrow plastic ssop ?40c to 85c lt1721cs#pbf lt1721cs#trpbf 1721 16-lead plastic so 0c to 70c lt1721is#pbf lt1721is#trpbf 1721i 16-lead plastic so ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
lt1720/lt1721 4 17201fc typical performance characteristics supply voltage (v) 2.5 v os and trip point voltage (mv) 3 2 1 0 C1 C2 C3 4.0 5.0 17201 g01 3.0 3.5 4.5 5.5 6.0 v trip + v os v trip C 25c v cm = 1v temperature (c) C3 v os and trip point voltage (mv) C1 1 3 C2 0 2 C25 25 100 17201 g02 C50 0 50 75 125 v trip + v os v trip C temperature (c) C50 3.6 3.8 4.2 25 75 17201 g03 0.2 0 C25 0 50 100 125 C0.2 C0.4 4.0 common mode input voltage (v) v cc = 5v input offset and trip voltages vs supply voltage input offset and trip voltages vs temperature input common mode limits vs temperature note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: if one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. note 3: the lt1720/lt1721 comparators include internal hysteresis. the trip points are the input voltage needed to change the output state in each direction. the offset voltage is de? ned as the average of v trip + and v trip C , while the hysteresis voltage is the difference of these two. note 4: the common mode rejection ratio is measured with v cc = 5v and is de? ned as the change in offset voltage measured from v cm = C0.1v to v cm = 3.8v, divided by 3.9v. note 5: the power supply rejection ratio is measured with v cm = 1v and is de? ned as the change in offset voltage measured from v cc = 2.7v to v cc = 6v, divided by 3.3v. electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v cm = 1v, c out = 10pf, v overdrive = 20mv, unless otherwise speci? ed. symbol parameter conditions min typ max units t pd differential propagation delay (note 9) between channels 0.3 1.0 ns t skew propagation delay skew (note 10) between t pdlh /t pdhl 0.5 1.5 ns t r output rise time 10% to 90% 2.5 ns t f output fall time 90% to 10% 2.2 ns t jitter output timing jitter v in = 1.2v p-p (6dbm), z in = 50 t pdlh v cm = 2v, f = 20mhz t pdhl 15 11 ps rms ps rms f max maximum toggle frequency v overdrive = 50mv, v cc = 3v v overdrive = 50mv, v cc = 5v 70.0 62.5 mhz mhz note 6: because of internal hysteresis, there is no small-signal region in which to measure gain. proper operation of internal circuity is ensured by measuring v oh and v ol with only 10mv of overdrive. note 7: propagation delay measurements made with 100mv steps. overdrive is measured relative to v trip . note 8: t pd cannot be measured in automatic handling equipment with low values of overdrive. the lt1720/lt1721 are 100% tested with a 100mv step and 20mv overdrive. correlation tests have shown that t pd limits can be guaranteed with this test, if additional dc tests are performed to guarantee that all internal bias conditions are correct. note 9: differential propagation delay is de? ned as the larger of the two: t pdlh = t pdlh(max) C t pdlh(min) t pdhl = t pdhl(max) C t pdhl(min) where (max) and (min) denote the maximum and minimum values of a given measurement across the different comparator channels. note 10: propagation delay skew is de? ned as: t skew = |t pdlh C t pdhl |
lt1720/lt1721 5 17201fc typical performance characteristics differential input voltage (v) C5 C7 input current (a) C6 C4 C3 C2 1234 2 17201 g04 C5 C4 C3 C2 C1 0 5 C1 0 1 25c v cc = 5v temperature (?c) C50 quiescent supply current per comparator (ma) 5.5 25 17201 g05 4.0 3.0 C25 0 50 2.5 2.0 6.0 5.0 4.5 3.5 75 100 125 v cc = 5v v cc = 3v supply voltage (v) 0 0 supply current per comparator (ma) 4 7 2 4 5 17201 g06 3 2 1 6 5 1 3 6 7 25c 125c C55c output load capacitance (pf) 0 delay (ns) 30 50 17201 g07 10 20 40 9 8 7 6 5 4 3 2 1 0 25c v step = 100mv overdrive = 20mv v cc = 5v rising edge (t pdlh ) falling edge (t pdhl ) temperature (c) C50 propagation delay (ns) 7.5 25 17201 g08 6.0 5.0 C25 0 50 4.5 4.0 8.0 7.0 6.5 5.5 75 100 125 v cc = 3v v cc = 3v v cc = 5v v cc = 5v t pdlh v cm = 1v v step = 100mv c load = 10pf overdrive = 5mv overdrive = 20mv supply voltage (v) 2.5 4.5 delay (ns) 5.0 4.0 4.0 5.0 17201 g09 3.0 3.5 4.5 5.5 6.0 rising edge (t pdlh ) falling edge (t pdhl ) 25c v step = 100mv overdrive = 20mv c load = 10pf output sink current (ma) 0 output voltage (v) 0.3 0.4 16 17201 g10 0.2 0.1 4 8 12 20 0.5 125c 25c 125c v cc = 2.7v v cc = 5v v cm = 1v v in = C15mv C55c output source current (ma) 0 output voltage relative to v cc (v) C0.4 C0.2 0.0 16 17201 g11 C0.6 C0.8 C1.0 4 8 12 20 125c C55c 25c 25c v cc = 2.7v v cc = 5v v cm = 1v v in = 15mv frequency (mhz) 0 7 8 10 30 no load 17201 g12 6 5 10 20 40 4 3 9 supply current per comparator (ma) 25c v cc = 5v c load = 20pf propagation delay vs load capacitance propagation delay vs temperature propagation delay vs supply voltage output low voltage vs load current output high voltage vs load current supply current vs frequency input current vs differential input voltage quiescent supply current vs temperature quiescent supply current vs supply voltage
lt1720/lt1721 6 17201fc pin functions lt1720 +in a (pin 1): noninverting input of comparator a. Cin a (pin 2): inverting input of comparator a. Cin b (pin 3): inverting input of comparator b. +in b (pin 4): noninverting input of comparator b. gnd (pin 5): ground. out b (pin 6): output of comparator b. out a (pin 7): output of comparator a. v cc (pin 8): positive supply voltage. lt1721 Cin a (pin 1): inverting input of comparator a. +in a (pin 2): noninverting input of comparator a. gnd (pins 3, 6): ground. out a (pin 4): output of comparator a . out b (pin 5): output of comparator b. +in b (pin 7): noninverting input of comparator b. Cin b (pin 8): inverting input of comparator b. Cin c (pin 9): inverting input of comparator c. +in c (pin 10): noninverting input of comparator c. v cc (pins 11, 14): positive supply voltage. out c (pin 12): output of comparator c. out d (pin 13): output of comparator d. +in d (pin 15): noninverting input of comparator d. Cin d (pin 16): inverting input of comparator d.
lt1720/lt1721 7 17201fc test circuits + C + C + C C + dut 1/2 lt1720 or 1/4 lt1721 15v p-p bandwidth-limited triangle wave ~ 1khz ltc203 1/2 lt1112 50 100k 100k 2.4k 10nf 1f 0.15f 1/2 lt1638 1/2 lt1638 100k 100k 200k 10k 10k 1000 s v hyst 1000 s v trip + 1000 s v trip C 1000 s v os 0.1f 50 50k v cm v cc + C 1/2 lt1112 17201 tc01 10nf 1f notes: lt1638, lt1112, ltc203s are powered from p 15v. 200kw pull-down protects ltc203 logic inputs when dut is not powered 15 3 2 14 16 9 1 8 10 6 7 11 ltc203 2 14 15 3 1 8 16 9 7 11 10 6 v trip test circuit response time test circuit C + C3v C100mv C5v pulse in 0v 0v 50 1n5711 400 130 25 50 +v cc C v cm Cv cm 50k dut 1/2 lt1720 or 1/4 lt1721 25 0.1f 17201 tc02 10 s scope probe (c in 10pf) 0.01f 0.01f 750 2n3866 v1* *v1 = C1000 ? (overdrive v trip + ) note: rising edge test shown. for falling edge, reverse lt1720 inputs
lt1720/lt1721 8 17201fc input voltage considerations the lt1720/lt1721 are speci? ed for a common mode range of C100mv to 3.8v when used with a single 5v supply. in general the common mode range is 100mv below ground to 1.2v below v cc . the criterion for this common mode limit is that the output still responds correctly to a small differential input signal. also, if one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits (a diode drop past either rail at 10ma input current) and the output will retain the correct polarity. when either input signal falls below the negative common mode limit, the internal pn diode formed with the substrate can turn on, resulting in signi? cant current ? ow through the die. an external schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. when both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least C400mv common mode. however, the offset and hysteresis in this mode will increase dramatically, to as much as 15mv each. the input bias currents will also increase. when both input signals are above the positive common mode limit, the input stage will become debiased and the output polarity will be random. however, the internal hysteresis will hold the output to a valid logic level, and because the biasing of each comparator is completely independent, there will be no impact on any other com- parator. when at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1s. the propagation delay does not increase signi? cantly when driven with large differential voltages. however, with low levels of overdrive, an apparent increase may be seen with large source resistances due to an rc delay caused by the 2pf typical input capacitance. applications information input protection the input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. external input protection cir- cuitry is only needed if currents would otherwise exceed these absolute maximums. the internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating. the lt1720/lt1721 input stage has general purpose internal esd protection for the human body model. for use as a line receiver, additional external protection may be required. as with most integrated circuits, the level of immunity to esd is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an esd pulse. unused inputs the inputs of any unused compartor should be tied off in a way that de? nes the output logic state. the easiest way to do this is to tie in + to v cc and in C to gnd. input bias current input bias current is measured with both inputs held at 1v. as with any pnp differential input stage, the lt1720/lt1721 bias current ? ows out of the device. with a differential input voltage of even just 100mv or so, there will be zero bias current into the higher of the two inputs, while the current ? owing out of the lower input will be twice the measured bias current. with more than two diode drops of differential input voltage, the lt1720/lt1721s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4a or less. see the typical performance curve input current vs differential input voltage.
lt1720/lt1721 9 17201fc high speed design considerations application of high speed comparators is often plagued by oscillations. the lt1720/lt1721 have 4mv of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mv. however, with the 2v/ns slew rate of the lt1720/lt1721 outputs, a 4mv step can be created at a 100 input source with only 0.02pf of output to input coupling. the pinouts of the lt1720/lt1721 have been arranged to minimize problems by placing the most sensitive inputs (invert- ing) away from the outputs, shielded by the power rails. the input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the outputs and the inputs. for multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and outputs, as illustrated in figure 1. applications information although both v cc pins are electrically shorted internal to the lt1721, they must be shorted together externally as well in order for both to function as shields. the same is true for the two gnd pins. the supply bypass should include an adjacent 10nf ce- ramic capacitor and a 2.2f tantalum capacitor no farther than 5cm away; use more capacitance if driving more than 4ma loads. to prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1k or less. the outputs of the lt1720/lt1721 are capable of very high slew rates. to prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. the lt1720/lt1721 can drive dc terminations of 250 or more, but lower characteristic impedance traces can be driven with series termination or ac termination topologies. hysteresis the lt1720/lt1721 include internal hysteresis, which makes them easier to use than many other comparable speed comparators. the input-output transfer characteristic is illustrated in figure 2 showing the de? nitions of v os and v hyst based upon the two measurable trip points. the hysteresis band makes the lt1720/lt1721 well behaved, even with slowly moving inputs. figure 1. typical topside metal for multilayer pcb layouts 17201 f01 (b) (a) figure 1a shows a typical topside layout of the lt1720 on such a multilayer board. shown is the topside metal etch including traces, pin escape vias, and the land pads for an so-8 lt1720 and its adjacent x7r 10nf bypass capacitor in a 1206 case. the ground trace from pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the out- puts. note the use of a common via for the lt1720 and the bypass capacitor, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. figure 1b shows a typical topside layout of the lt1721 on a multilayer board. in this case, the power and ground traces have been extended to the bottom of the device solely to act as high frequency shields between input and output traces. figure 2. hysteresis i/o characteristics v hyst (= v trip + C v trip C ) v hyst /2 v ol 17201 f02 v oh v trip C v trip + $ v in = v in + C v in C v trip + + v trip C 2 v os = v out 0
lt1720/lt1721 10 17201fc the exact amount of hysteresis will vary from part to part as indicated in the speci? cations table. the hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. a key advantage of the lt1720/ lt1721 is the signi? cant reduction in these effects, which is important whenever an lt1720/lt1721 is used to detect a threshold crossing in one direction only. in such a case, the relevant trip point will be all that matters, and a stable offset voltage with an unpredictable level of hysteresis, as seen in competing comparators, is of little value. the lt1720/lt1721 are many times better than prior compara- tors in these regards. in fact, the cmrr and psrr tests are performed by checking for changes in either trip point to the limits indicated in the speci? cations table. because the offset voltage is the average of the trip points, the cmrr and psrr of the offset voltage is therefore guaranteed to be at least as good as those limits. this more stringent test also puts a limit on the common mode and power supply dependence of the hysteresis voltage. additional hysteresis may be added externally. the rail-to-rail outputs of the lt1720/lt1721 make this more predictable than with ttl output comparators due to the lt1720/lt1721s small variability of v oh (output high voltage). to add additional hysteresis, set up positive feedback by adding additional external resistor r3 as shown in figure 3. resistor r3 adds a portion of the output to the threshold set by the resistor string. the lt1720/lt1721 pulls the outputs to the supply rail and ground to within 200mv of the rails with light loads, and to within 400mv with heavy loads. for the load of most circuits, a good applications information model for the voltage on the right side of r3 is 300mv or v cc C 300mv, for a total voltage swing of (v cc C 300mv) C 300mv = v cc C 600mv. with this in mind, calculation of the resistor values needed is a two-step process. first, calculate the value of r3 based on the additional hysteresis desired, the output voltage swing, and the impedance of the primary bias string: r3 = (r1 || r2)(v cc C 0.6v)/(additional hysteresis) additional hysteresis is the desired overall hysteresis less the internal 3.5mv hysteresis. the second step is to recalculate r2 to set the same av- erage threshold as before. the average threshold before was set at v th = (v ref )(r1)/(r1 + r2). the new r2 is calculated based on the average output voltage (v cc /2) and the simpli? ed circuit model in figure 4. to assure that the comparators noninverting input is, on average, the same v th as before: r2 = (v ref C v th )/(v th /r1 + (v th C v cc /2)/r3) for additional hysteresis of 10mv or less, it is not uncommon for r2 to be the same as r2 within 1% resistor tolerances. this method will work for additional hysteresis of up to a few hundred millivolts. beyond that, the impedance of r3 is low enough to effect the bias string, and adjust- ment of r1 may also be required. note that the currents through the r1/r2 bias string should be many times the input currents of the lt1720/lt1721. for 5% accuracy, the current must be at least 120a(6a i b 0.05); more for higher accuracy. figure 3. additional external hysteresis C + 1/2 lt1720 input 17201 f03 r2 v ref r3 r1 figure 4. model for additional hysteresis calculations C + 1/2 lt1720 17201 f04 r2 a v ref v th r3 v cc 2 v average = r1
lt1720/lt1721 11 17201fc interfacing the lt1720/lt1721 to ecl the lt1720/lt1721 comparators can be used in high speed applications where emitter-coupled logic (ecl) is deployed. to interface the outputs of the lt1720/lt1721 to ecl logic inputs, standard ttl/cmos to ecl level translators such as the 10h124, 10h424 and 100124 can be used. these components come at a cost of a few nanoseconds additional delay as well as supply currents of 50ma or more, and are only available in quads. a faster, simpler and lower power translator can be constructed with resistors as shown in figure 5. figure 5a shows the standard ttl to positive ecl (pecl) resistive level translator. this translator cannot be used for the lt1720/lt1721, or with cmos logic, because it depends on the 820 resistor to limit the output swing (v oh ) of the all-npn ttl gate with its so-called totem-pole output. the lt1720/lt1721 are fabricated in a complementary bipolar process and their output stage has a pnp driver that pulls the output nearly all the way to the supply rail, even when sourcing 10ma. figure 5b shows a three resistor level translator for interfac- ing the lt1720/lt1721 to ecl running off the same supply rail. no pull-down on the output of the lt1720/lt1721 is needed, but pull-down r3 limits the v ih seen by the pecl gate. this is needed because ecl inputs have both a minimum and maximum v ih speci? cation for proper operation. resistor values are given for both ecl interface types; in both cases it is assumed that the lt1720/lt1721 operates from the same supply rail. figure 5c shows the case of translating to pecl from an lt1720/lt1721 powered by a 3v supply rail. again, resis- tor values are given for both ecl interface types. this time four resistors are needed, although with 10kh/e, r3 is not needed. in that case, the circuit resembles the standard ttl translator of figure 5a, but the function of the new resistor, r4, is much different. r4 loads the lt1720/lt1721 output when high so that the current ? owing through r1 doesnt forward bias the lt1720/lt1721s internal esd clamp diode. although this diode can handle 20ma without damage, normal operation and performance of the output stage can be impaired above 100a of forward current. r4 prevents this with the minimum additional power dissipation. applications information finally, figure 5d shows the case of driving standard, nega- tive-rail, ecl with the lt1720/lt1721. resistor values are given for both ecl interface types and for both a 5v and 3v lt1720/lt1721 supply rail. again, a fourth resistor, r4 is needed to prevent the low state current from ? owing out of the lt1720/lt1721, turning on the internal esd/substrate diodes. not only can the output stage functionality and speed suffer, but in this case the substrate is common to all the comparators in the lt1720/lt1721, so operation of the other comparator(s) in the same package could also be affected. resistor r4 again prevents this with the minimum additional power dissipation. for all the dividers shown, the output impedance is about 110. this makes these fast, less than a nanosecond, with most layouts. avoid the temptation to use speedup capacitors. not only can they foul up the operation of the ecl gate because of overshoots, they can damage the ecl inputs, particularly during power-up of separate supply con? gurations. the level translator designs assume one gate load. multiple gates can have signi? cant i ih loading, and the transmis- sion line routing and termination issues also make this case dif? cult. ecl, and particularly pecl, is valuable technology for high speed system design, but it must be used with care. with less than a volt of swing, the noise margins need to be evaluated carefully. note that there is some degradation of noise margin due to the 5% resistor selections shown. with 10kh/e, there is no temperature compensation of the logic levels, whereas the lt1720/lt1721 and the circuits shown give levels that are stable with temperature. this will degrade the noise margin over temperature. in some con? gurations it is possible to add compensation with diode or transistor junctions in series with the resistors of these networks. for more information on ecl design, refer to the eclips data book (dl140), the 10kh system design handbook (hb205) and pecl design (an1406), all from on semiconductor (www.onsemi.com).
lt1720/lt1721 12 17201fc applications information figure 5 5v 5v 180 270 820 10kh/e r2 v cc r3 r1 10kh/e 100k/e v cc 5v or 5.2v 4.5v r1 510 620 r2 180 180 r3 750 510 (a) standard ttl to pecl translator (b) lt1720/lt1721 output to pecl translator lsttl 1/2 lt1720 r2 v cc 3v r3 r4 r1 10kh/e 100k/e v cc 5v or 5.2v 4.5v r1 300 330 r2 180 180 r3 omit 1500 (c) 3v lt1720/lt1721 output to pecl translator 1/2 lt1720 r4 560 1000 r4 v ee v cc r3 17201 f05 r2 r1 ecl family 10kh/e v ee C5.2v r1 560 270 v cc 5v 3v r2 270 510 r3 330 300 (d) lt1720/lt1721 output to standard ecl translator 1/2 lt1720 r4 1200 330 100k/e C4.5v 680 330 5v 3v 270 390 300 270 1500 430 do not use for lt1720/lt1721 level translation. see text
lt1720/lt1721 13 17201fc circuit description the block diagram of one comparator in the lt1720/lt1721 is shown in figure 6. there are differential inputs (+in/Cin), an output (out), a single positive supply (v cc ) and ground (gnd). all comparators are completely independent, shar- ing only the power and ground pins. the circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary common-emitter output stage. all of the internal signal paths utilize low voltage swings for high speed at low power. the input stage topology maximizes the input dynamic range available without requiring the power, complex- ity and die area of two complete input stages such as are found in rail-to-rail input comparators. with a 2.7v supply, the lt1720/lt1721 still have a respectable 1.6v of input common mode range. the differential input volt- age range is rail-to-rail, without the large input currents found in competing devices. the input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the C100mv common mode voltage limit. the internal hysteresis is implemented by positive, nonlin- ear feedback around a second gain stage. until this point, the signal path has been entirely differential. the signal path is then split into two drive signals for the upper and lower output transistors. the output transistors are con- nected common emitter for rail-to-rail output operation. the schottky clamps limit the output voltages at about 300mv from the rail, not quite the 50mv or 15mv of linear applications information technologys rail-to-rail ampli?ers and other products. but the output of a comparator is digital, and this output stage can drive ttl or cmos directly. it can also drive ecl, as described earlier, or analog loads as demonstrated in the applications to follow. the bias conditions and signal swings in the output stages are designed to turn their respective output transistors off faster than on. this nearly eliminates the surge of current from v cc to ground that occurs at transitions, keeping the power consumption low even with high output-toggle frequencies. the low surge current is what keeps the power consump- tion low at high output-toggle frequencies. the frequency dependence of the supply current is shown in the typical performance characteristics. just 20pf of capacitive load on the output more than triples the frequency dependent rise. the slope of the no-load curve is just 32a/mhz. with a 5v supply, this current is the equivalent of charging and discharging just 6.5pf. the slope of the 20pf load curve is 133a/mhz, an addition of 101a/mhz, or 20a/mhz-v, units that are equivalent to picofarads. the lt1720/lt1721 dynamic current can be estimated by adding the external capacitive loading to an internal equivalent capacitance of 5pf to 15pf, multiplied by the toggle frequency and the supply voltage. because the capacitance of routing traces can easily approach these values, the dynamic current is dominated by the load in most circuits. figure 6. lt1720/lt1721 block diagram C + C + C + C + +in Cin a v1 a v2 nonlinear stage out gnd 17201 f06 v cc + 3 + 3
lt1720/lt1721 14 17201fc speed limits the lt1720/lt1721 comparators are intended for high speed applications, where it is important to understand a few limitations. these limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. there are no signi?cant input speed limits except the shunt capacitance of the input nodes. if the 2pf typical input nodes are driven, the lt1720/lt1721 will respond. the output speed is constrained by two mechanisms, the ? rst of which is the slew currents available from the output transistors. to maintain low power quiescent op- eration, the lt1720/lt1721 output transistors are sized to deliver 25ma to 45ma typical slew currents. this is suf?cient to drive small capacitive loads and logic gate inputs at extremely high speeds. but the slew rate will slow dramatically with heavy capacitive loads. because the propagation delay (t pd ) de?nition ends at the time the output voltage is halfway between the supplies, the ?xed slew current actually makes the lt1720/lt1721 faster at 3v than 5v with 20mv of input overdrive. another manifestation of this output speed limit is skew, the difference between t pdlh and t pdhl . the slew currents of the lt1720/lt1721 vary with the process variations of the pnp and npn transistors, for rising edges and falling edges respectively. the typical 0.5ns skew can have either polarity, rising edge or falling edge faster. again, the skew will increase dramatically with heavy capacitive loads. the skews of comparators in a single package are corre- lated, but not identical. besides some random variability, there is a small (100ps to 200ps) systematic skew due to physical parasitics of the packages. for the lt1720 so-8, comparator a, whose output is adjacent to the v cc pin, will have a relatively faster rising edge than comparator b. likewise, comparator b, by virtue of an output adjacent to the ground pin will have a relatively faster falling edge. similar dependencies occur in the lt1721 s16, while the systemic skews in the smaller msop and ssop packages are half again as small. of course, if the capacitive loads on the two comparators of a single package are not identical, the differential timing will degrade further. applications information the second output speed limit is the clamp turnaround. the lt1720/lt1721 output is optimized for fast initial response, with some loss of turnaround speed, limiting the toggle frequency. the output transistors are idled in a low power state once v oh or v ol is reached by detecting the schottky clamp action. it is only when the output has slewed from the old voltage to the new voltage, and the clamp circuitry has settled, that the idle state is reached and the output is fully ready to transition again. this clamp turnaround time is typically 8ns for each direction, resulting in a maximum toggle frequency of 62.5mhz, or a 125mb data rate. with higher frequencies, dropout and runt pulses can occur. increases in capacitive load will increase the time needed for slewing due to the limited slew currents and the maximum toggle frequency will decrease further. for higher toggle frequency applications, refer to the lt1715, whose output stage can toggle at 150mhz typical. the internal speed limits manifest themselves as disper- sion. all comparators have some degree of dispersion, de?ned as a change in propagation delay versus input overdrive. the propagation delay of the lt1720/lt1721 will vary with overdrive, from a typical of 4.5ns at 20mv overdrive to 7ns at 5mv overdrive (typical). the lt1720/ lt1721s primary source of dispersion is the hysteresis stage. as a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. with 5mv of overdrive, the lt1720/lt1721 are faster with a 5v supply than with a 3v supply, the opposite of what is true with 20mv overdrive. this is due to the internal speed limit, because the gain stage is faster at 5v than 3v due primarily to the reduced junction capacitances with higher reverse voltage bias. in many applications, as shown in the following examples, there is plenty of input overdrive. even in applications providing low levels of overdrive, the lt1720/lt1721 are fast enough that the absolute dispersion of 2.5ns (= 7 C 4.5) is often small enough to ignore.
lt1720/lt1721 15 17201fc the gain and hysteresis stage of the lt1720/lt1721 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. this internal self-latch can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. it is therefore highly immune to disturbances from other parts of the circuit, either in the same comparator, on the supply lines, or from the other comparator(s) in the same package. once a high speed signal trips the hysteresis, the output will respond, after a ?xed propagation delay, without regard to these external in?uences that can cause trouble in nonhysteretic comparators. v trip test circuit the input trip points are tested using the circuit shown in the test circuits section that precedes this applications information section. the test circuit uses a 1khz triangle wave to repeatedly trip the comparator being tested. the lt1720/lt1721 output is used to trigger switched capaci- tor sampling of the triangle wave, with a sampler for each direction. because the triangle wave is attenuated 1000:1 and fed to the lt1720/lt1721s differential input, the sampled voltages are therefore 1000 times the input trip voltages. the hysteresis and offset are computed from the trip points as shown. crystal oscillators a simple crystal oscillator using one comparator of an lt1720/lt1721 is shown on the ? rst page of this data sheet. the 2k-620 resistor pair set a bias point at the comparators noninverting input. the 2k-1.8k-0.1f path sets the inverting input node at an appropriate dc aver- age level based on the output. the crystals path provides resonant positive feedback and stable oscillation occurs. although the lt1720/lt1721 will give the correct logic output when one input is outside the common mode range, additional delays may occur when it is so operated, open- ing the possibility of spurious operating modes. therefore, the dc bias voltages at the inputs are set near the center of the lt1720/lt1721s common mode range and the 220 resistor attenuates the feedback to the noninvert- ing input. the circuit will operate with any at-cut crystal from 1mhz to 10mhz over a 2.7v to 6v supply range. applications information as the power is applied, the circuit remains off until the lt1720/lt1721 bias circuits activate, at a typical v cc of 2v to 2.2v (25c), at which point the desired frequency output is generated. the output duty cycle for this circuit is roughly 50%, but it is affected by resistor tolerances and, to a lesser extent, by comparator offsets and timings. if a 50% duty cycle is required, the circuit of figure 7 creates a pair of comple- mentary outputs with a forced 50% duty cycle. crystals are narrow-band elements, so the feedback to the noninverting input is a ?ltered analog version of the square wave output. changing the noninverting reference level can therefore vary the duty cycle. c1 operates as in the previous example, whereas c2 creates a complementary output by compar- ing the same two nodes with the opposite input polarity. a1 compares band-limited versions of the outputs and biases c1s negative input. c1s only degree of freedom to respond is variation of pulse width; hence the outputs are forced to 50% duty cycle. again, the circuit operates from 2.7v to 6v, and the skew between the edges of the two outputs are shown in figure 8. there is a slight duty cycle dependence on comparator loading, so equal capacitive and resistive loading should be used in critical applications. this circuit works well because of the two matched delays and rail-to-rail style outputs of the lt1720. figure 7. crystal oscillator with complementary outputs and 50% duty cycle C + C + C + c1 1/2 lt1720 c2 1/2 lt1720 a1 lt1636 v cc 2.7v to 6v 2k 620 220 1mhz to 10mhz crystal (at-cut) 100k 100k 17201 f07 1.8k 2k 1k 0.1f 0.1f 0.1f output output ground case
lt1720/lt1721 16 17201fc the circuit in figure 9 shows a crystal oscillator circuit that generates two nonoverlapping clocks by making full use of the two independent comparators of the lt1720. c1 oscillates as before, but with a lower reference level, c2s output will toggle at different times. the resistors set the degree of separation between the outputs high pulses. with the values shown, each output has a 44% high and 56% low duty cycle, suf?cient to allow 2ns between the high pulses. figure 10 shows the two outputs. applications information the optional a1 feedback network shown can be used to force identical output duty cycles. the steady state duty cycles of both outputs will be 44%. note, though, that the addition of this network only adjusts the percentage of time each output is high to be the same, which can be important in switching circuits requiring identical settling times. it cannot adjust the relative phases between the two outputs to be exactly 180 apart, because the signal at the input node driven by the crystal is not a pure sinusoid. figure 8. timing skew of figure 7s circuit supply voltage (v) 2.5 output skew (ps) 4.5 6.0 1000 800 600 400 200 0 1720/21 f08 3.5 5.5 3.0 4.0 5.0 figure 10. nonoverlapping outputs of figure 9s circuit figure 9. crystal-based nonoverlapping 10mhz clock generator C + C + C + c1 1/2 lt1720 c2 1/2 lt1720 a1 lt1636 v cc 2.7v to 6v 2k 620 220 10mhz crystal (at-cut) 100k 100k 2.2k 1.3k 2k 1k 17201 f09 0.1f 0.1f 0.1f output 0 output 1 ground case optional see text 20ns/div q1 2v/div q0 2v/div 17201 f10
lt1720/lt1721 17 17201fc timing skews for a number of reasons, the lt1720/lt1721s superior timing speci? cations make them an excellent choice for applications requiring accurate differential timing skew. the comparators in a single package are inherently well matched, with just 300ps t pd typical. monolithic construc- tion keeps the delays well matched vs supply voltage and temperature. crosstalk between the comparators, usually a disadvantage in monolithic duals and quads, has minimal effect on the lt1720/lt1721 timing due to the internal hysteresis, as described in the speed limits section. the circuits of figure 11 show basic building blocks for differential timing skews. the 2.5k resistance interacts with the 2pf typical input capacitance to create at least 4ns delay, controlled by the potentiometer setting. a differential and a single-ended version are shown. in the differential con?guration, the output edges can be smoothly scrolled through t = 0 with negligible interaction. 3ns delay detector it is often necessary to measure comparative timing of pulse edges in order to determine the true synchronicity of clock and control signals, whether in digital circuitry or in high speed instrumentation. the circuit in figure 12 applications information is a delay detector which will output a pulse when signals x and y are out of sync (speci? cally, when x is high and y is low). note that the addition of an identical circuit to detect the opposite situation (x low and y high) allows for full skew detection. comparators u1a and u1b clean up the incoming signals and render the circuit less sensitive to input levels and slew rates. the resistive divider network provides level shifting for the downstream comparators common mode input range, as well as offset to keep the output low except during a decisive event. when the upstream comparators outputs can overcome the resistively generated offset (and hysteresis), comparator u1c performs a boolean x*_y function and produces an output pulse (see figure 13). the circuit will give full output response with input delays down to 3ns and partial output response with input delays down to 1.8ns. capacitor c1 helps ensure that an imbal- ance of parasitic capacitances in the layout will not cause common mode excursions to result in differential mode signal and false outputs. 1 1 make sure the input levels at x and y are not too close to the 0.5v threshold set by the r8Cr9 divider. if you are still getting false outputs, try increasing c1 to 10pf or more. you can also look for the problem in the impedance balance (r5 || r6 = r7) at the inputs of u1c. increasing the offset by lowering r5 will help reject false outputs, but r7 should also be lowered to maintain impedance balance. for ease of design and parasitic matching, r7 can be replaced by two parallel resistors equal to r5 and r6. lt1720 differential p 4ns relative skew c in c in c in c in v ref 2.5k 2.5k input lt1720 0ns to 4ns single-ended delay c in c in 17201 f11 v ref input c in c in C + C + C + C + figure 11. building blocks for timing skew generation with the lt1720
lt1720/lt1721 18 17201fc applications information figure 12. 3ns delay detector with logarithmic pulse stretcher 5v C + u1a 1/4 lt1721 y 51* r8* 4.53k 5v 5v 17201 f12 0.1f c1 5.6pf 0.33f r9 487* + C u1b 1/4 lt1721 + C u1c 1/4 lt1721 x 1v x 0v 51* c2 540pf ** r7 261* z C + u1d 1/4 lt1721 301* r5 1.82k* r6 301* 5v r4 30* r3 1* v off r2 1k* 475* l 301* 301* result of x and not y + C r1 499* decay capture optional logarithmic pulse stretcher (see text) v c v in 1n5711 delay detector 1v y 0v 5v z 0v * 1% metal film resistor ** 270pf s 2 for reduced lead inductance figure 13. output pulse due to delay of y input pulse
lt1720/lt1721 19 17201fc optional logarithmic pulse stretcher the fourth comparator of the quad lt1721 can be put to work as a logarithmic pulse stretcher. this simple circuit can help tremendously if you dont have a fast enough oscilloscope (or control circuit) to easily capture 3ns pulse widths (or faster). when an input pulse occurs, c2 is charged up with a 180ns capture 2 time constant. the hysteresis and 10mv offset across r3 are overcome within the ? rst nanosecond 3 , switching the comparator output high. when the input pulse subsides, c2 discharges with a 540ns time constant, keeping the comparator on until the decay overrides the 10mv offset across r3 minus hysteresis. because of this exponential decay, the output pulse width will be proportional to the logarithm of the input pulse width. it is important to bypass the circuits v cc well to avoid coupling into the resistive divider. r4 keeps the quiescent input voltage in a range where forward leakage of the diode due to the 0.4v v ol of the driving comparator is not a problem. neglecting some effects 4 , the output pulse is related to the input pulse as: t out = 2 ? l n {v ch ? [1 C exp (Ct p / 1 )]/(v off C v h /2)} C 1 ? l n [v ch /(v ch C v off C v h /2)] + t p (1) where t p = input pulse width t out = output pulse width 1 = r1 || r2 ? c2 the capture time constant 2 = r2 ? c2 the decay time constant v off = 10mv the voltage drop across r1 v h = 3.5mv lt1721 hysteresis v c = v in C v fdiode the input pulse voltage after the diode drop v ch = v c ? r2/(r1 + r2) the effective source voltage for the charge applications information for simplicity, with t p < 1 , and neglecting the very slight delay in turn-on due to offset and hysteresis, the equation can be approximated by: t out = 2 ? l n [(v ch ? t p / 1 )/(v off C v h /2)] (2) for example, an 8ns input pulse gives a 1.67s output pulse. doubling the input pulse to 16ns lengthens the output pulse by 0.37s. doubling the input pulse again to 32ns adds another 0.37s to the output pulse, and so on. the rate of 0.37s per octave falls out of the above equation as: t out /octave = 2 ? l n(2) (3) there is 0.01s jitter 5 in the output pulse which gives an uncertainty referred to the input pulse of less than 2% (60ps resolution on a 3ns pulse with a 60mhz oscilloscopenot bad!). the beauty of this circuit is that it gives resolution precisely where its hardest to get. the jitter is due to a combination of the slow decay of the last few millivolts on c2 and the 4nv/ hz noise and 400mhz bandwidth of the lt1721 input stage. increasing the offset across r3 or decreasing 2 will decrease this jitter at the expense of dynamic range. the circuit topology itself is extremely fast, limited theo- retically only by the speed of the diode, the capture time constant 1 and the pulse source impedance. figure 14 shows results achieved with the implementation shown, compared to a plot of equation (1). the low end is limited by the delivery time of the upstream comparators. as the input pulse width is increased, the log function is con- strained by the asymptotic rc response but, rather than becoming clamped, becomes time linear. thus, for very long input pulses the third term of equation (1) dominates and the circuit becomes a 3s pulse stretcher. 2 so called because the very fast input pulse is captured, for later examination, as a charge on the capacitor. 3 assuming the input pulse slew rate at the diode is in? nite. this effective delay constant, about 0.4% of 1 or 0.8ns, is the second term of equation 1, below. driven by the 2.5ns slew-limited lt1721, this effective delay will be 2ns. 4 v c is dependent on the lt1721 output voltage and nonlinear diode characteristics. also, the thevenin equivalent charge voltage seen by c2 is boosted slightly by r2 being terminated above ground. 5 output jitter increases with inputs pulse widths below ~3ns.
lt1720/lt1721 20 17201fc you dont need expensive equipment to con? rm the actual overall performance of this circuit. all you need is a respect- able waveform generator (capable of >~100khz), a splitter, a variety of cable lengths and a 20mhz or 60mhz oscilloscope. split a single pulse source into different cable lengths and then into the delay detector, feeding the longer cable into the y input (see figure 15). a 6 foot cable length difference will create a ~9.2ns delay (using 66% propagation speed rg-58 cable), and should result in easily measured 1.70s output pulses. a 12 foot cable length difference will result in ~18.4ns delay and 2.07s output pulses. the difference applications information in the two output pulse widths is the per-octave response of your circuit (see equation (3)). shorter cable length dif- ferences can be used to get a plot of circuit performance down to 1.5ns (if any), which can then later be used as a lookup reference when you have moved from quantifying the circuit to using the circuit. (note there is a slight aberration in performance below 10ns. see figure 14.) as a ? nal check, feed the circuit with identical cable lengths and check that it is not producing any output pulses. 10ns triple overlap generator the circuit of figure 16 utilizes an lt1721 to generate three overlapping outputs whose pulse edges are separated by 10ns as shown. the time constant is set by the rc net- work on the output of comparator a. comparator b and d trip at ? xed percentages of the exponential voltage decay across the capacitor. the 4.22k feed-forward to the c comparators inverting input keeps the delay differences the same in each direction despite the exponential nature of the rc networks voltage. there is a 15ns delay to the ? rst edge in both directions, due to the 4.5ns delay of two lt1721 comparators, plus 6ns delay in the rc network. this starting delay is shortened somewhat if the pulse was shorter than 40ns because the rc network will not have fully settled; however, the 10ns edge separations stay constant. the values shown utilize only the lowest 75% of the supply voltage span, which allows it to work down to 2.7v supply. the delay differences grow a couple nanoseconds from 5v to 2.7v supply due to the ? xed v ol /v oh drops which grow as a percentage at low supply voltage. to keep this effect to a minimum, the 1k pull-up on comparator a provides equal loading in either state. fast waveform sampler figure 17 uses a diode-bridge-type switch for clean, fast waveform sampling. the diode bridge, because of its inherent symmetry, provides lower ac errors than other semiconductor-based switching technologies. this circuit features 20db of gain, 10mhz full power bandwidth and 100v/c baseline uncertainty. switching delay is less than 15ns and the minimum sampling window width for full power response is 30ns. figure 14. log pulse stretcher output pulse vs input pulse t pulse (ns) t out stretched (s) 14 12 10 8 6 4 2 0 1 100 1000 10000 17201 f14 10 measured equation 1 figure 15. rg-58 cable with velocity of propogation = 66%; delay at y = (n C 1) ? 1.54ns splitter 2v 0v circuit of figure 12 n foot cable 1 foot cable nanosecond input range microsecond output range x y l t out (see text) 17201 f15
lt1720/lt1721 21 17201fc applications information figure 16. 10ns triple overlap generator v cc C + u1a 1/4 lt1721 C + u1b 1/4 lt1721 C + u1d 1/4 lt1721 C + u1c 1/4 lt1721 681 681 1.37k v cc 909 215 v cc input outputs v ref 100pf 453 1k 750 v cc 10ns 10ns 10ns 17201 f16 10ns 4.22k figure 17. fast waveform sampler using the lt1720 for timing-skew compensation C + 5v 2.2k 2.2k input p 100mv full scale 1k lt1227 909 100 output p 1v full scale 5v ac balance 3pf 3.6k 1.5k 0.1f c in c in 2k 2k 10pf skew comp 2.5k 1.1k 1.1k 1.1k 1.1k 820 820 mrf501 mrf501 lm3045 11 9 6 8 dc balance 500 51 51 10 7 680 C5v 17201 f17 13 = 1n5711 = ca3039 diode array (substrate to C5v) C + 1/2 lt1720 C + 1/2 lt1720 sample command
lt1720/lt1721 22 17201fc the input waveform is presented to the diode bridge switch, the output of which feeds the lt1227 wideband ampli?er. the lt1720 comparators, triggered by the sample com- mand, generate phase-opposed outputs. these signals are level shifted by the transistors, providing complementary bipolar drive to switch the bridge. a skew compensation trim ensures bridge-drive signal simultaneity within 1ns. the ac balance corrects for parasitic capacitive bridge im- balances. a dc balance adjustment trims bridge offset. the trim sequence involves grounding the input via 50 and applying a 100khz sample command. the dc balance is adjusted for minimal bridge on vs off variation at the output. the skew compensation and ac applications information balance adjustments are then optimized for minimum ac disturbance in the output. finally, unground the input and the circuit is ready for use. voltage-controlled clock skew generator it is sometimes necessary to generate pairs of identical clock signals that are phase skewed in time. further, it is desirable to be able to set the amount of time skew via a tuning voltage. figure 18s circuit does this by utilizing the lt1720 to digitize phase information from a varactor-tuned time domain bridge. a 0v to 2v control signal provides 10ns of output skew. this circuit operates from a 2.7v to 6v supply. figure 18. voltage-controlled clock skew 17201 f18 C + c2 1/2 lt1720 v cc 2.7v to 6v v cc q q a fixed output mv-209 varactor diode 2.5k clock input 2.5k 0.1f 2.2f 0.005f skewed fixed 10ns trim 36pf ? 1.82m* 6.2m* 1.1m 100k 200pf 2k* C + c1 1/2 lt1720 skewed output input 0v to 2v p 10ns skew 2.5k* 14k 2k 12pf ? 1m 1m v cc C + a1 lt1077 * 1% film resistor ** sumida cd43-100 ? polystyrene, 5% = 1n4148 = 74hc04 + lt1317 v in sw 47f l1** v c gnd fb +
lt1720/lt1721 23 17201fc applications information coincidence detector high speed comparators are especially suited for interfac- ing pulse-output transducers, such as particle detectors, to logic circuitry. the matched delays of a monolithic dual are well suited for those cases where the coincidence of two pulses needs to be detected. the circuit of figure 19 is a coincidence detector that uses an lt1720 and discrete components as a fast and gate. the reference level is set to 1v, an arbitrary threshold. only when both input signals exceed this will a coincidence be detected. the schottky diodes from the comparator outputs to the base of the mrf-501 form the and gate, while the other two schottkys provide for fast turn-off. a logic and gate could instead be used, but would add considerably more delay than the 300ps contributed by this discrete stage. this circuit can detect coincident pulses as narrow as 3ns. for narrower pulses, the output will degrade gracefully, responding, but with narrow pulses that dont rise all the way to high before starting to fall. the decision delay is 4.5ns with input signals 50mv or more above the refer- ence level. this circuit creates a ttl compatible output but it can typically drive cmos as well. for a more detailed description of the operation of this circuit, see application note 75, pages 10 and 11. figure 19. a 3ns coincidence detector 5v 3.9k 1k 0.1f 51 51 300 300 5v 5v 4 s 1n5711 mrf501 output ground case lead coincidence comparators 300ps and gate 17201 f19 1/2 lt1720 C + C + 1/2 lt1720
lt1720/lt1721 24 17201fc simplified schematic Cin +in gnd 17201 ss output v cc 150 150
lt1720/lt1721 25 17201fc package description dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ 2.38 p 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1203 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.675 p 0.05 3.5 p 0.05 package outline 0.25 p 0.05 0.50 bsc s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 o 0 o C 8 o typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 p .005 recommended solder pad layout .045 p .005 .050 bsc .030 p .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1720/lt1721 26 17201fc package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 0307 rev f 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 p 0.0508 (.004 p .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 o C 6 o typ detail a detail a gauge plane 12 3 4 4.90 p 0.152 (.193 p .006) 8 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 o 0 o C 8 o typ .008 C .010 (0.203 C 0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 C .157 (3.810 C 3.988) note 3 16 15 14 13 .386 C .394 (9.804 C 10.008) note 3 .228 C .244 (5.791 C 6.197) 12 11 10 9 s16 0502 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 p .005 recommended solder pad layout .045 p .005 .050 bsc .030 p .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1720/lt1721 27 17201fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 p .004 (0.38 p 0.10) s 45 o 0 o C 8 o typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 p .0015 .045 p .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
lt1720/lt1721 28 17201fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1998 lt 0908 rev c ? printed in usa related parts typical application part number description comments lt1016 ultrafast precision comparator industry standard 10ns comparator lt1116 12ns single supply ground-sensing comparator single supply version of lt1016 lt1394 7ns, ultrafast, single supply comparator 6ma single supply comparator lt1671 60ns, low power, single supply comparator 450a single supply comparator lt1715 4ns, 150mhz dual comparator similar to the lt1720 with independent input/output supplies lt1719 4.5ns single supply 3v/5v comparator single comparator similar to the lt1720/lt1721 pulse stretcher for detecting short pulses from a single sensor, a pulse stretcher is often required. the circuit of figure 20 acts as a one-shot, stretching the width of an incoming pulse to a consistent 100ns. unlike a logic one-shot, this lt1720-based circuit requires only 100pv-s of stimulus to trigger. the circuit works as follows: comparator c1 functions as a threshold detector, whereas comparator c2 is con?gured as a one-shot. the ?rst comparator is prebiased with a threshold of 8mv to overcome comparator and system offsets and establish a low output in the absence of an input signal. an input pulse sends the output of c1 high, which in turn latches c2s output high. the output of c2 is fed back to the input of the ?rst comparator, causing regeneration and latching both outputs high. timing capacitor c now begins charging through r and, at the end of 100ns, c2 resets low. the output of c1 also goes low, latching both outputs low. a new pulse at the input of c1 can now restart the process. timing capacitor c can be increased without limit for longer output pulses. this circuit has an ultimate sensitivity of better than 14mv with 5ns to 10ns input pulses. it can even detect an avalanche generated test pulse of just 1ns duration with sensitivity better than 100mv. 6 it can detect short events better than the coincidence detector of figure 14 because the one-shot is con?gured to catch just 100mv of upward movement from c1s v ol , whereas the coincidence detectors 3ns speci?cation is based on a full, legitimate logic high, without the help of a regenerative one-shot. 6 see linear technology application note 47, appendix b. this circuit can detect the output of the pulse generator described after 40db attenuation. C + C + pulse source c1 1/2 lt1720 c2 1/2 lt1720 50 51 6.8k 1n5711 24 15k r 1k 2k 2k 17201 f20 2k c 100pf 0.01f output 100ns 5v figure 20. a 1ns pulse stretcher

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